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nju6433b ver.2012-10-23 -1- 1/4 duty lcd driver general description the nju6433b is a 1/4 duty lcd driver for segment type lcd panel. the lcd driver consists of 4-common and 50-segment drives up to 200 segments. the nju6433b is useful for the digital tuning system or others segment type display driver. features 50 segment drivers duty ratio 1/4 (up to 200-segments) serial data transmission (shift clock 2mhz max.) oscillation circuit on-chip (ext ernal resistance required) display off function (inhb terminal) operating voltage 2.4 to 5.5v lcd driving voltage 6.5v max. package outline chip, qfp64-h1 c-mos technology block diagram package outline nju6433bc preliminary NJU6433BFH1 vlcd inhb ce vss com1 com4 osc1 seg50 seg1 vdd oscillation divider shift register2 50-bit input select shift register1 50-bit input select shift register4 50-bit input select shift register3 50-bit input select decoder shift register control circuit input select circuit osc2 dat a mode scl latch circuit / segment driver lcd driving voltage circuit common driver reset circuit
nju6433b ver.2012-10-23 - 2 - pad location chip center : x=0 m, y=0 m chip size : x=3.20 mm, y=3.20 mm chip thickness : 400 m pad size : x=99.2 m, y=99.2 m pad pitch : 171.2 m pad coordinates chip size 3.20 x 3.20 mm(chip center x=0 m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= my= m pad no. terminal x= my= m 1 seg 1 -1279 -1437 25 seg 25 1437 81 49 seg 49 -1437 1280 2 seg 2 -1107 -1437 26 seg 26 1437 253 50 seg 50 -1437 1109 3 seg 3 -936 -1437 27 seg 27 1437 424 51 osc 1 -1437 937 4 seg 4 -765 -1437 28 seg 28 1437 595 52 osc 2 -1437 766 5 seg 5 -594 -1437 29 seg 29 1437 766 53 v dd -1437 595 6 seg 6 -423 -1437 30 seg 30 1437 937 54 v ss -1437 424 7 seg 7 -251 -1437 31 seg 31 1437 1109 55 v lcd -1437 253 8 seg 8 -80 -1437 32 seg 32 1437 1280 56 ce -1437 81 9 seg 9 91 -1437 33 seg 33 1280 1437 57 scl -1437 -90 10 seg 10 262 -1437 34 seg 34 1109 1437 58 data -1437 -261 11 seg 11 433 -1437 35 seg 35 937 1437 59 mode -1437 -432 12 seg 12 605 -1437 36 seg 36 766 1437 60 inhx -1437 -603 13 seg 13 776 -1437 37 seg 37 595 1437 61 com 4 -1437 -775 14 seg 14 947 -1437 38 seg 38 424 1437 62 com 3 -1437 -946 15 seg 15 1118 -1437 39 seg 39 253 1437 63 com 2 -1437 -1117 16 seg 16 1289 -1437 40 seg 40 81 1437 64 com 1 -1437 -1288 17 seg 17 1437 -1288 41 seg 41 -90 1437 18 seg 18 1437 -1117 42 seg 42 -261 1437 19 seg 19 1437 -946 43 seg 43 -432 1437 20 seg 20 1437 -775 44 seg 44 -603 1437 21 seg 21 1437 -603 45 seg 45 -775 1437 22 seg 22 1437 -432 46 seg 46 -946 1437 23 seg 23 1437 -261 47 seg 47 -1117 1437 24 seg 24 1437 -90 48 seg 48 -1288 1437 1 16 48 33 17 32 49 64 y x
nju6433b ver.2012-10-23 -3- pin configuration terminal description no. symbol function 1~50 seg 1 ~seg 50 lcd segment output terminals 61~64 com 4 ~com 1 lcd common output terminals 51 52 osc 1 osc 2 oscillation terminals : external resistance is connected to these terminals. 53 v dd power supply (+5v) 54 v ss power supply (0v) 55 v lcd power supply for lcd driving the relation : 1.3v dd |v dd - v lcd |, v ss v lcd must be maintained. 56 ce chip enable signal input terminal : "h" : lcd display data and mode setting data input "l" : disable fall edge : lcd display data latch 57 scl serial data transmission clock input terminal : lcd display and mode setting data are input synchronized scl clock signal rise edge. 58 data serial data input terminal data input timing : scl clock rise edge 59 mode data or mode select terminal "h" : data input mode "l" : lcd display data input mode (refer the mode setting table for mode setting contents) 60 inhb display-off control terminal : when display goes to off, the display data in the shift-register is retained. "h" : display-on "l" : display-off b
nju6433b ver.2012-10-23 - 4 - functional description (1) operation of each block (1-1) oscillation circuit the oscillation circuit operates by connecting exte rnal resistance (capacitance is incorporated). this circuit provides the clock sign al to both common and segment drivers. (1-2) divider circuit this circuit divides the oscillating signal to generate the common and segment timing. (1-3) shift-register when the ce terminal is "h" (enable mode), the di splay data is transferred to the shift-register synchronized by the shift clock on the scl terminal. (1-4) latch circuit and segment driver when the ce signal falling, the display data is la tched, and the data controls the segment signal of display-on/off. (1-5) common driver the common driver generates driving waveform to common terminal. (1-6) reset circuit the reset circuit is type of detectable voltage. it resets internal circuit when the power turns on.
nju6433b ver.2012-10-23 -5- (2) mode setting the mode setting is composed of 4-bit, and selects the sh ift register that writes the display data by writing data in the mode setting register. (refer to "(4) data input timing" for details.) when the data (1,1,1,1) is input, ?0? (all displa y-off) is written in all shift registers. the mode setting register is selected by ce="h" and mode="h". the data is latched at the rising edge of the scl, and selected at falling edge of the ce. table 1. mode setting table mode data description 1 (msb) 1,0,0,0 (lsb) shift register 1 is selected. 2 0,1,0,0 shift register 2 is selected. 3 1,1,0,0 shift register 3 is selected. 4 0,0,1,0 shift register 4 is selected. 5 1,0,1,0 all shift register (1~4) is sele cted, and data is written continuously. f 1,1,1,1 all shift register is ?0?. (3) correspondence of the transfer data and output terminal the display data is written by ce="h" and mode="l" . the data is latched at the rising edge of the scl, and written at falling edge of the ce. the correspondence of the data and the output terminals is as follows. output terminal com 1 com 2 com 3 com 4 output terminal com 1 com 2 com 3 com 4 seg 1 d1 d2 d3 d4 seg 26 d101 d102 d103 d104 seg 2 d5 d6 d7 d8 seg 27 d105 d106 d107 d108 seg 3 d9 d10 d11 d12 seg 28 d109 d110 d111 d112 seg 4 d13 d14 d15 d16 seg 29 d113 d114 d115 d116 seg 5 d17 d18 d19 d20 seg 30 d117 d118 d119 d120 seg 6 d21 d22 d23 d24 seg 31 d121 d122 d123 d124 seg 7 d25 d26 d27 d28 seg 32 d125 d126 d127 d128 seg 8 d29 d30 d31 d32 seg 33 d129 d130 d131 d132 seg 9 d33 d34 d35 d36 seg 34 d133 d134 d135 d136 seg 10 d37 d38 d39 d40 seg 35 d137 d138 d139 d140 seg 11 d41 d42 d43 d44 seg 36 d141 d142 d143 d144 seg 12 d45 d46 d47 d48 seg 37 d145 d146 d147 d148 seg 13 d49 d50 d51 d52 seg 38 d149 d150 d151 d152 seg 14 d53 d54 d55 d56 seg 39 d153 d154 d155 d156 seg 15 d57 d58 d59 d60 seg 40 d157 d158 d159 d160 seg 16 d61 d62 d63 d64 seg 41 d161 d162 d163 d164 seg 17 d65 d66 d67 d68 seg 42 d165 d166 d167 d168 seg 18 d69 d70 d71 d72 seg 43 d169 d170 d171 d172 seg 19 d73 d74 d75 d76 seg 44 d173 d174 d175 d176 seg 20 d77 d78 d79 d80 seg 45 d177 d178 d179 d180 seg 21 d81 d82 d83 d84 seg 46 d181 d182 d183 d184 seg 22 d85 d86 d87 d88 seg 47 d185 d186 d187 d188 seg 23 d89 d90 d91 d92 seg 48 d189 d190 d191 d192 seg 24 d93 d94 d95 d96 seg 49 d193 d194 d195 d196 seg 25 d97 d98 d99 d100 seg 50 d197 d198 d199 d200 correspondence of the transfer data and segment status transfer data segment status ?h? on ?l? off
nju6433b ver.2012-10-23 - 6 - (4) data input timing the format of data is as follows. the mode data is input by 4-bit of msb first, and after the shift register is selected, the display data is written - mode 1 : shift register 1 (d1~d50) - mode 2 : shift register 2 (d51~d100) - mode 3 : shift register 3 (d101~d150) - mode 4 : shift register 4 (d151~d200) ce scl data mode d1 2 3 4 5 6 7 8 mode data display data x 50-bit 44 45 46 47 48 49 50 1 0 0 0 (msb) (lsb) ce scl data mode 51 52 53 54 55 56 57 58 mode data display data x 50-bit 94 95 96 97 98 99 100 0 1 0 0 ce scl data mode 101 102 103 104 105 106 107 108 mode data display data x 50-bit 144 145 146 147 148 149 150 1 1 0 0 ce scl data mode 151 152 153 154 155 156 157 158 mode data display data x 50-bit 194 195 196 197 198 199 200 0 0 1 0
nju6433b ver.2012-10-23 -7- - mode 5 : shift register 1~4 (d1~d200) - mode f : shift register 1~4 all ?0? note 1) all of display data should be transmitted wi thin 30ms to keep the display quality, because huge display data d1 to d200 are transmitted at 4 times totally. note 2) data is latched at the rising edge of the scl. note 3) mode data and display data are executed at the falling edge of the ce. note 4) in case of less than 4-bit data, the mode data remains the lsb side of the previous mode data. note 5) in case of over 4-bit data, the mode data is valid the previous 4-bit of the falling edge of the ce. note 6) in case of less than 50-bit data, the display data remains the last part of the previous display data. note 7) in case of over 50-bit data, the display data is valid the previous 50-bit of the falling edge of the ce. (5) initialization by power on reset the nju6433b incorporates the reset circuit of the detect able voltage type, and when the power supply is turned on, it automatically initializes it (reset). wh en the vdd becomes 90% of the working voltage, the reset signal is generated internally. reset is completed after 2ms, and it becomes usually status. the serial data is able to transmit after completed reset. (5-1) status of power on reset 1. mode setting release (nonselective status) 2. shift register : all ?0? 3. latch circuit : all ?0? ce scl data mode d1 2 3 4 5 6 7 8 mode data display data x 200-bit 194 195 196 197 198 199 200 1 0 1 0 ce scl data mode mode data 1 1 1 1 90% internal reset signal reset operation period (over 2ms) usually status vdd
nju6433b ver.2012-10-23 - 8 - (6) lcd panel drive (6-1) lcd driving volyage generation circuit the lcd driving voltage generation circuit generates lcd driving bias voltages v1 and v2 from input voltage vdd-vlcd. it is generated by the bleeder resistance in ic, and after impedance is converted by the voltage follower, it is supplied to the lcd driving circuit. t he vdd and vlcd terminal requires external capacitors for bias voltage stabilization for display quality as shown in below. v dd v 2 v 1 v lcd nju6433b internal vlcd + + v dd v lcd
nju6433b ver.2012-10-23 -9- absolute maximum ratings ta = 2 5 c parameter symbol conditions ratings unit operating voltage (1) v ddmax v dd te r m i n a l , ta = 2 5 c -0.3~+7.0 v operating voltage (2) v lcd v dd -6.5~v ss v input voltage (1) v 1(1) ce, scl, data, mode, inhb terminals ta = 2 5 c -0.3~+7.0 v input voltage (2) v 1(2) osc 1 , osc 2 terminals -0.3~v dd +0.3 v output voltage v 0 osc 1 , osc 2 terminals -0.3~v dd +0.3 v output current (1) i o(1) seg 1 ~seg 50 terminals 100 ua output current (2) i o(2) com 1 ~com 4 terminals 1.0 ma power dissipation p dmax ta = 8 5 c 300 mw operating temperature t opr -30~+85 c storage temperature t stg -40~+125 c note 1) all voltage values are specified as v ss = 0v. note 2) if the lsi is used on condition above the absolut e maximum ratings, the lsi may be destroyed. using the lsi within electrical characteristics is strong ly recommended for normal operation. use beyond the electric characteristics conditions w ill cause malfunction and poor reliability. note 3) the relation v dd > v ss v lcd must be maintained. note 4) decoupling capacitor should be connected between v dd and v ss due to the stabilized operation for the lsi. electrical characteristics ? dc characteristics parameter symbol conditions min typ max unit no te operating voltage (1) v dd v dd terminal 2.4 5.0 5.5 v operating voltage (2) v lcd v lcd terminal v ss v dd -6.5 v "h" input voltage v ih 0.7v dd v dd v "l? input voltage v il ce, scl, data, mode, inhb v ss 0.3v dd v "h" input current v ih v i =v dd 5 ua "l" input current v il ce,scl, data,mode, inhb v i =v ss 5 ua "h" output voltage (1) v oh(1) i o =-10ua v dd -1.0 v "l? output voltage (1) v ol(1) seg 1 ~seg 50 i o =+10ua v lcd +1.0 v middle level voltage 1/3(1) v ms1/3 i o = 10ua v 1 -1.0 v 1 v 1 +1.0 v middle level voltage 2/3(1) v ms2/3 seg 1 ~seg 50 i o = 10ua v 2 -1.0 v 2 v 2 +1.0 v 1 "h" output voltage (2) v oh(2) i o =-100ua v dd -0.6 v "l" output voltage (2) v ol(2) com 1 ~com 4 i o =+100ua v lcd +0.6 v middle level voltage 1/3(2) v mc1/3 i o = 100ua v 1 -0.6 v 1 v 1 +0.6 v middle level voltage 2/3(2) v mc2/3 com 1 ~com 4 i o = 100ua v 2 -0.6 v 2 v 2 +0.6 v 1 oscillating frequency range f rng osc 1 , osc 2 terminals 25 200 khz oscillating frequency f osc osc 1 , osc 2 terminals r=140k ? , v dd =5v 115 130 145 khz operating current (1) i ss v ss terminal, v dd =5v 50 80 ua operating current (2) i lcd v lcd terminal, v dd =5v, v lcd =v dd -6.5v 15 25 ua hysteresis voltage v h ce, scl, data, mode, inhb v dd =5v 0.3 v note 1) v 1 =1/3|v dd -v lcd |, v 2 =2/3|v dd -v lcd | (v dd =5v 10%, v lcd =v dd -6.5v, ta=25 c ) v 2 v 1 1/3|v dd -v lcd | 2/3|v dd -v lcd | v dd v lcd
nju6433b ver.2012-10-23 - 10 - ? ac characteristics parameter symbol conditions min typ max unit "l" clock pulse width t wcll scl 0.25 us "h" clock pulse width t wclh scl 0.25 us data set-up time t ds scl, data 0.25 us data hold time t dh scl, data 0.25 us ce set-up time t sce ce, data 1.0 us ce hold time (1) t hdce ce, data 1.0 us ce hold time (2) t hcle ce, scl 1.25 us mode set-up time t smd mode, ce 0.25 us mode hold time t hmd mode, ce 0.25 us "l" chip enable pulse width t wcel ce 4.0 us rise time tr scl 50 ns fall time tf scl 50 ns power supply rise time t rdd v dd 0.1 10 ms power supply off time t off v dd 1 ms ? input timing characteristics (v dd =5v 10%, ta=25 c ) v dd 4.5v 0.2v t rdd t off 0.2v 0.2v 5.0v scl ce dat a mode twcll twclh tf tr tds tdh thcle d0 d1 thdce tsce tsmd thmd twcel
nju6433b ver.2012-10-23 -11- ? lcd driving waveform(1/4duty ? 1/3bias) com 1 com 2 com 3 ?off? segment output corresponds to com 1 , com 2 , com 3 and com 4 ?on? segment output corresponds to com 1 ?on? segment output corresponds to com 2 ?on? segment output corresponds to com 1 and com 2 ?on? segment output corresponds to com 3 ?on? segment output corresponds to com 1 and com 3 ?on? segment output corresponds to com 2 and com 3 ?on? segment output corresponds to com 1 , com 2 and com 3 com 4 ?on? segment output corresponds to com 4 ?on? segment output corresponds to com 2 and com 4 ?on? segment output corresponds to com 1 , com 2 , com 3 and com 4 v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss v0 v1 v2 vss 1frame = fosc/1024 (hz)
nju6433b ver.2012-10-23 - 12 - application circuit example) vdd=5v, vlcd=6.5v example) vdd=3v, vlcd=5v example) vdd=3v, vlcd=3v lcd panel 200 segments com 1 com 2 com 3 com 4 seg 1 seg 2 seg 3 seg 4 seg 5 : : seg 48 seg 49 seg 50 ce scl data mode inhb v dd v ss v lcd com 1 com 2 com 3 com 4 seg 1 seg 2 seg 3 seg 4 seg 5 : : seg 48 seg 49 seg 50 osc1 osc2 nju6433b 5 v v ss -1.5 v + + cpu 140k ?

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